Programmable integrated circuits (ICs), such as field programmable gate arrays (FPGAs), are user configurable ICs capable of implementing various digital logic operations. FPGAs include programmable logic circuits such as configurable logic blocks (CLBs) arranged in rows and columns, input/output blocks (IOBs) surrounding the CLBs, and programmable interconnect lines that extend between the rows and columns of CLBs. The CLBs, IOBs, and interconnect lines are configured to implement a particular design according to configuration data stored in configuration memory of the programmable IC.
The versatility of programmable ICs is advantageous in applications, such as those requiring high availability, high reliability, or functional safety, where remote reconfiguration is preferred over physical replacement. However, with shrinkage of device geometry, atmospheric radiation such as neutrons can cause an error in bi-stable circuits known as a single event upset (SEU). When a single heavy ion strikes a silicon substrate, it loses energy through the creation of free electron hole pairs. This results in a dense ionized track in the local region, generating a current pulse that can upset the circuit. This is known as a single event upset (SEU) or soft error. An SEU can also be caused by alpha particles. Alpha particles are generated when a neutron strikes a silicon substrate. The alpha particles travel through the substrate and generate charge clusters within a limited silicon volume. Alpha particles can be generated from high energy neutrons as well as neutrons that have lost enough kinetic energy to be at thermal equilibrium with the operating environment. Alpha particles can also be generated through the decay of semiconductor packages that contain a small amount of radioactive contaminants.
In a programmable IC, an SEU may induce errors in configuration memory cells used to configure programmable logic circuits to perform specific functions, thereby changing the configuration of a user circuit design implemented by the programmable logic circuits. An SEU may additionally or alternatively induce errors by changing the value of a bi-stable circuit (e.g., a flip flop or latch) included in a user circuit design that is implemented by the programmable logic circuits. For ease of reference, an error induced in configuration memory by an SEU may be referred to as a configuration upset. An error induced in a bi-stable circuit of a user circuit design may be referred to as a logic upset.
Generally, logic upsets induced by SEU are mitigated by implementing three redundant copies of a circuit along with a majority voter to ensure that a correct value is output while a logic upset occurs in one of the redundant copies. This is known as triple modular redundancy (TMR). However, TMR increases both resource requirements and power consumption of a circuit threefold.